Senior Graduate or Engineer with Specialization in Analog Microelectronics
The IFIC-Valencia and ETSE-University of Valencia announce the call for 1 contract with an extension of 2 years for a Senior Graduate or Engineer with Specialization in Analog Microelectronics. The contract is financed by the MCINN with European funds NextGenerationEU (PRTR-C17.I01) and by the Generalitat Valenciana in the Program of Complementary Plans for R+D+i in Astrophysics and High Energy Physics (ASFAE/2022/031).
The objective of this contract is the design of the GRIT readout ASIC and the tasks expected to be performed are:
- Review of the current PLAS V2 design to assess whether the specifications in terms of ENOB (~11 bits) and analog sampling bandwidth (200 MHz) can be achieved improving the present design.
− Define the actions on the PLAS ASIC concept/implementation to achieve the required specifications for GRIT.
− Extension or modification of the PLAS V2 design to include a filter on the input signal or a method to use the ASIC pre-amplifier reset system to reduce baseline effects at high count rates.
− Definition and design of the ASIC test system and protocols.
